SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling

The SUAVE project aims to introduce object-oriented and genericity extensions into VHDL in a way that does not disturb the existing language or its use. Designers regularly define abstract data types by using aspects of VHDL’s type system, subprograms, and packages. They also use VHDL’s genericity mechanism to parameterize component and entity declarations with formal generic constants. The SUAVE approach builds on these basic mechanisms by strengthening the facilities for encapsulation and adding an inheritance mechanism. It also extends the genericity mechanism by allowing formal generics types and by allowing generics to be specified in the interfaces of subprograms and packages. The SUAVE extensions are based on the features of Ada-95. They allow units to be re-used in a much wider variety of contexts without modifying the original code. By choosing an incremental and evolutionary approach to extensions, SUAVE avoids major additions to the language that would complicate choice of mechanisms for expressing a design. This paper outlines the SUAVE extensions and illustrates their use through some examples.